The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for thermal cycling and gradient management in three-dimensional stacked architectures.
Reliability and thermal characteristics of three-dimensional (3D) integrated circuits are considered among the most important challenges in current computing systems. 3D integrated circuits present unique thermal challenges due to differences in geometry, power dissipation, and heat removal patterns. 3D integrated circuits exhibit higher temperatures and more prominent thermal gradients within the layers, as well as new vertical thermal gradients that do not exist in two-dimensional (2D) integrated circuits. A thermal gradient is a rate of temperature change with distance. The combination of higher temperatures and thermal gradients exacerbate reliability problems in the stacked architectures.
Thermal cycling, that is, how temperature changes over time, also becomes an important challenge in this setting due to various reasons, such as:                1. Thinned silicon (Si) causes inherent mechanical and reliability challenges.        2. Increased number of neighbors, resulting in more complex heat and thermal cycling effects.        3. Combination of different materials used, such as Copper (Cu), Silicon (Si), Tungsten (W), oxides, dielectrics, or the like, with different thermal expansion and mechanical characteristics.        4. Thermal expansion prominent in different directions in all dimensions, specifically vertical expansion that could break the horizontal back-end (BE) wires.        
As activity levels fluctuate across computing units in 3D integrated circuits, thermal cycling effects threaten the reliability of 3D integrated circuit architectures more than 2D integrated circuit counterparts due to the above reasons. Without specialized techniques, 3D integrated circuits are prone to reliability problems caused by thermal cycling.
Moreover, most thermal management techniques in a 3D integrated circuits attempt to invert the heating patterns in consecutive layers in the 3D integrated circuit architecture as an attempt to minimize the peak temperatures. As the hotspot regions align, the corresponding temperatures increase even further since the heat cannot be drained to the heat sink through vertically overlapping blockages. A major side effect of such thermal management is that the thermal management creates severe thermal gradients in vertical and horizontal directions, both between neighbor blocks on the same layer and the block that are neighbors in a vertical direction. The inverted heating patterns make thermal cycling and mechanical stress effects even worse because the inverted heating patterns maximize the mechanical forces in the opposite directions, which can cause warping and cracking. Even further, through silicon via (TSV) and wiring layers are perpendicular to each other and any expansion of TSVs can easily crack the silicon and wiring layers that the TSVs make contact with.